Buffer Sizing for Multimedia Flows in Packet-Switching NoCs

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Buffering ⊲ Packet Switching in Single Buffer Bufferless Packet Switching ⊲

1. Aggarwal, A., Vitter, J.S.: The input/output complexity of sorting and related problems. Commun. ACM 31, 1116–1127 (1988) 2. Arge, L.A.: External memory data structures. In: Abello, J., Pardalos, P.M., Resende, M.G.C. (eds.) Handbook of Massive Data Sets, pp. 313–357. Kluwer, Dordrecht (2002) 3. Arge, L.A.: The Buffer Tree: A technique for designing batched external data structures. Algorith...

متن کامل

Output - Buffer ATM Packet Switching for Integrated

| In this paper, we give an overview of the basic design principles and trade-oos of output-buuer ATM switching. Output-buuer switches give optimal performance in terms of ooering band-width guarantees to individual ows. Bandwidth scheduling and memory bandwidth requirements are also described.

متن کامل

Output-Buffer ATM Packet Switching for Integrated-Services Communication Networks

|In this paper, we give an overview of the basic design principles and trade-o s of output-bu er ATM switching. Outputbu er switches give optimal performance in terms of o ering bandwidth guarantees to individual ows. Bandwidth scheduling and memory bandwidth requirements are also described.

متن کامل

Buffer scaling for optical packet switching networks with shared RAM

According to a historical rule of thumb, which is widely used in routers, the buffer size of each output link of a router should be set to the product of the bandwidth and the average round-trip time. However, it is very difficult to satisfy this buffer requirement for ultra-high-speed dense wavelength division multiplexing (DWDM) networks with the current technology. Recently, many researchers...

متن کامل

Déjà Vu Switching for Multiplane NoCs

In chip-multiprocessors (CMPs) the network-onchip (NoC) carries cache coherence and data messages. These messages may be classified into critical and non-critical messages. Hence, instead of having one interconnect plane to serve all traffic, power can be saved if the NoC is split into two planes: a fast plane dedicated to the critical messages and a slower, more power-efficient plane dedicated...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Journal of Integrated Circuits and Systems

سال: 2008

ISSN: 1872-0234,1807-1953

DOI: 10.29292/jics.v3i1.281